1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor device, more particularly to a method of forming a spacer on side-walls of a titanium polycide gate.
2. Description of the Related Art
Mostly polysilicon or polysilicon/tungsten silicide has been used for gate material of an MOSFET. As the line width of a gate is decreased due to the enhanced integrity of semiconductor devices, it is difficult to satisfy low resistance in the gate having fine line width with the foregoing polysilicon or polysilicon/tungsten silicide material.
Therefore, to satisfy low resistance in the fine line width, a Ti-polycide gate consisting of a stack structure of polysilicon and titanium silicide TiSi2 has been highlighted as for the gate material. The titanium silicide has relatively excellent properties required as a gate material such as low resistivity, high melting point, easiness in manufacturing of thin film as well as pattern, and thermal stability.
Meanwhile, the increase of resistance in the gate having decreased line width can be prevented by varying the material of the gate. As noted in the art, the short channel effect caused by the decrease of channel length can be prevented by using the LDD(Lightly doped drain) structure.
Hereinafter, a method of manufacturing a semiconductor device having the conventional titanium polycide gate will e described with reference to FIGS. 1A to 1C.
Referring to FIG. 1A, a semiconductor substrate 1 is provided, a gate oxide layer 2, a polysilicon layer 3, a titanium silicide layer TiSi2 4 and a patterned hard mask 5 are successively deposited on the semiconductor substrate 1. The titanium silicide layer 4, the polysilicon layer 3 and the gate oxide layer are etched by using the hard mask 5 as a etching mask, thereby forming a Ti-polycide gate 10.
To recover the damage caused during the etching step, to remove polysilicon residues, and to improve reliability of the gate oxide layer 2, a gate re-oxidation process is performed. As a result, a re-oxidation layer 11 is formed on side-walls of the Ti-polycide gate 10 and on a surface of the substrate 1. At this time, the gate re-oxidation process is performed at temperature of below 750° C. so that abnormal oxidation at an exposed portion of the titanium silicide layer 4 is prevented.
To form the LLD structure, a selected impurity(not shown) is implanted with low concentration into a portion of the substrate 1 of both sides of the gate 10.
Referring to FIG. 1B, an oxide layer 12 is deposited on the resultant by the low pressure chemical vapor deposition process(“LPCVD”) using SiH4 gas and N2O gas, and a nitride layer 13 is deposited on the oxide layer 12.
Referring to FIG. 1C, the nitride layer 13, the oxide layer 12 and the re-oxidation layer 11 are blanket-etched, thereby forming a spacer 20 on side-walls of the gate 10 and the hard mask 5.
Although not shown in the drawing, a selected impurity is implanted with high concentration into the exposed substrate region 1 by using the spacer 20 and the gate 10 as a mask, thereby completing the semiconductor device having the T-polycide gate and the LDD structure.
However, according to the foregoing conventional method of fabricating the semiconductor device, the abnormal oxidation of the titanium silicide layer 4 during deposition of the oxide layer 12 is occurred. As a result, an abnormal oxidation 15 is formed on side-walls of the titanium silicide layer 15, thereby degrading the property of the gate 10. The above result is caused by depositing the oxidation layer 12 at temperature of 780° C. that is higher than 750° C., and by using the N2O gas as a reaction gas, which has excellent oxidizing power compared to O2.
Moreover, profile of the gate 10 is heterogeneous and the heterogeneity of the profile of the gate 10 has a bad influence upon profile of the spacer 20. Therefore, it is difficult to obtain the reliability of device.